The currently produced type of ferroelectric memories, which are one kind of capacitor elements, uses a so-called planar structure in which the lower electrodes are larger than the upper electrodes, and has a capacity of 1 to 64 kbit. On the other hand, the focus of current development is on ferroelectric memories with a large capacity of 256 kbit to 4 Mbit, which use a so-called stacked structure in which the lower electrodes are smaller than the upper electrodes. It is increasingly expected that these ferroelectric memories with stacked structure are suitable to vastly improve the integration degree and to improve the reliability of non-volatile memories.
Conventional ferroelectric memories with stacked structure are known, in which irregularities in the surface of an insulating film are evened out by CMP (chemical mechanical polishing) to form a ferroelectric film not affected by irregularities of the lower layer and achieve a ferroelectric memory with high reliability (see for example JP H10-321628). The following is an explanation of a conventional method for manufacturing a ferroelectric memory with stacked structure, with reference to FIGS. 11A to 11F. FIG. 11A to FIG. 11F show sections of a memory cell array portion during the steps of manufacturing a conventional ferroelectric memory.
First, as shown in FIG. 11A, isolation regions 1 are formed on a semiconductor substrate 10, and a high-concentration impurity diffusion layer 2 is formed between the isolation regions 1. Then, an interlayer insulation film 4 is formed on the isolation regions 1 and the impurity diffusion layer 2, and contact plugs 3 that are electrically connected to the impurity diffusion layers 2 are formed in the interlayer insulation film 4. A layered film of a titanium nitride barrier layer and a platinum film serving as a first conductive film 5 is formed on the interlayer insulation film 4 and the contact plugs 3. Next, a resist pattern is formed on the first conductive film 5, and the first conductive film 5 is patterned by dry etching taking the resist pattern as a mask, to form lower electrodes 6 on the contact plugs 3, as shown in FIG. 11B.
Then, as shown in FIG. 11C, covering the lower electrodes 6 and the interlayer insulating film 4, a burying insulating film 8 made of silicon oxide (SiO2) is formed over the entire wafer surface. Next, as shown in FIG. 11D, the insulating film 8 is polished by CMP to planarize its surface, and the surfaces of the insulating film 8 and the lower electrodes 6 are polished until they are flush, as shown in FIG. 11E. Then, as shown in FIG. 11F, a ferroelectric film 9 serving as a capacitive insulating film and a second conductive film 20 (made of platinum or the like) are formed in that order on top of the insulating film 8 and the lower electrodes 6.
Next, although not shown in the drawings, the second conductive film 20 and the ferroelectric film 9 are patterned by dry etching with a resist pattern as the mask to form upper electrodes. After that, ordinarily, a capacitor interlayer insulating film is formed, and after a wiring step and a protective film formation step, the ferroelectric memory is obtained.
With this ferroelectric memory, the surface area of the lower electrodes 6 is smaller than the surface area of the ferroelectric and the upper electrodes above it, and the capacitance of the capacitors is determined by the lower electrodes 6. That is to say, the lower electrode 6 becomes a “capacitance-defining area” that determines the capacity (area) of the capacitor. Moreover, with the structure shown in FIG. 11F, the ferroelectric film 9 is formed on a surface whose irregularities due to the lower electrodes 6 have been planarized, so that the film quality is favorable.
With the above-described manufacturing method, when polishing the insulating film 8 by CMP, the lower electrode 6 is uniformly exposed across the entire wafer surface, and in order to avoid insufficient polishing, which may lead to variations in the capacitive properties of the ferroelectric memory, it is necessary to over-polish to some degree, while giving consideration to the in-plane uniformity of the CMP.
However, since a layer of a precious metal such as Pt that is difficult to polish is formed on the surface of the lower electrodes 6, recesses may be formed near the lower electrodes 6 due to the planarization by CMP, leading to a slight protrusion of the lower electrodes 6. When over-polishing in this situation, polishing stress concentrates in the lower electrodes 6, and the lower electrodes 6 may peel off or scratches may be formed in the lower electrodes 6. For this reason, it was necessary to optimize the polishing time such that there is no insufficient polishing and no scratches are formed, which becomes a factor narrowing the degree of freedom (window) for setting the polishing parameters.
As a result of studying this problem, the inventors found that these scratches tend to occur primarily in regions of low wiring pattern density, with isolated patterns, such as isolated metal wiring, measurement marks, and alignment marks, rather than in regions of high wiring pattern density, such as in memory array portions in which the lower electrodes are integrated.
Referring to FIGS. 12A to 12E, the following is an explanation of a process in which scratches occur. FIGS. 12A to 12A show sections of a metal wiring portion in the steps of manufacturing a ferroelectric memory shown in FIGS. 11A to 11A. The steps in FIGS. 12A to 12E correspond to the steps in FIGS. 11A to 11E respectively, and are performed at the same time.
First, as shown in FIG. 12A, a high-concentration impurity diffusion layer 2 is formed on a semiconductor substrate 10. On top of the impurity diffusion layer 2, an interlayer insulation film 4 and a first conductive film 5 are formed in that order. Then, the first conductive film 5 is patterned by dry etching with a resist pattern as the mask to form a metal wiring 7, as shown in FIG. 12B. Then, as shown in FIG. 12C, a burying insulating film 8 made of silicon oxide (SiO2) is formed over the entire wafer surface, burying the metal wiring 7 and the interlayer insulation film 4, as shown in FIG. 12C. Next, as shown in FIG. 12D, the insulating film 8 is polished by CMP to planarize its surface.
In regions with a low density of wiring patterns, such as portions in which an isolated metal wiring 7 is arranged, the volume of the polished insulating film 8 is smaller, so that in the polishing step, they are polished faster than regions with a high density of wiring patterns, as in the memory cell array portion. Therefore, the leveling of steps progresses faster, and the metal wiring 7 is exposed more quickly from the insulating film 8 than the lower electrodes 6 (see FIG. 11D). In this situation, an over-polishing is performed until the surfaces of the insulating film 8 and the lower electrodes 6 are flush, as shown in FIG. 11E. As a result, recesses are formed near the metal wiring 7, which is already exposed, causing the metal wiring 7 to stick out. Thus, polishing stress concentrates at the metal wiring 7, and the metal wiring 7 may be peeled off, as shown in FIG. 12E. This peeled metal wiring 7 may become a cause for scratches, resulting in a chain of peeling of metal wiring 7 and occurrence of scratches.
This phenomenon occurs due to differences in the density of memory cells and differences in the occupied area on the wafer. FIG. 13 schematically illustrates the situation when the surface of the lower electrodes 6 is exposed by CMP in the process of manufacturing an element including memory array portions with different array surface area. FIGS. 13A1 to 13C1 are plan views showing the arrangement of the lower electrodes 6 for a memory cell array portion with large array surface area, a memory cell array portion with small array surface area, and a region without lower electrodes 6 (referred to below as “peripheral circuit portion”). FIGS. 13A2 to 13C2 show sections of these regions. These regions are all polished at the same time.
When the surfaces of the lower electrodes 6 in the memory cell array portion with large array surface area are exposed, as shown in FIG. 13A3, recesses are formed near the lower electrodes 6 in the memory cell array portion with small array surface area, as shown in FIG. 13B3, and the lower electrodes 6 are peeled off. In the peripheral circuit portion shown in FIG. 13C3, the polishing speed for the flat insulating film 8 (referred to as a “solid film” in the following) is dominant, so that the global level difference becomes large. Here, “global level difference” refers to the difference between the maximum film thickness and the minimum film thickness of the film remaining on the wafer surface.
The following is a quantitative explanation of this phenomenon with reference to FIG. 14, modeling the polishing state at the memory cell array portions with large and small array surface area and the peripheral circuit portion.
In the graph of FIG. 14, the horizontal axis marks the polishing time, and the vertical axis marks the thickness of the remaining film after polishing by CMP of an insulating film (of 400 nm thickness) formed on the lower electrodes (of 300 nm thickness). The thickness of the remaining film is plotted for the memory cell array portion with large array surface area, the one with small array surface area, and for the peripheral circuit portion. Note, however, that for the peripheral circuit portion, the thickness of the remaining film on the interlayer insulation film 4 is shown. Looking at how the thickness of the remaining film changes with the polishing time, it can be seen that the peripheral circuit portion is polished uniformly with the polishing speed of the solid film (200 nm/min). On the other hand, it can be seen that at the ferroelectric memory cell area portions in which the lower electrodes 6 are provided underneath, there is a time period at the start of the polishing during which the leveling of steps is accelerated, followed by a time period during which the polishing is carried out at the polishing speed of the solid film.
As shown in FIG. 14, in order to expose all of the lower electrodes 6, the polishing time needs to be set to 90 sec (1.5 min), because 90 sec are necessary in order to ensure that the thickness of the remaining film in the memory cell array portion with large array surface area becomes 0 nm. In this case, the memory array cell portion with small array surface area is over-polished for 0.5 min, and recesses of 100 nm (=200 nm/min×0.5 min) are formed near the lower electrodes 6. This becomes a cause for peeling of the lower electrodes 6. On the other hand, the peripheral circuit portion is polished by 300 nm (=200 nm/min×1.5 min). Consequently, the remaining film thicknesses a, b and c of the insulating film shown in FIGS. 13A3 to 13C3 will be a=300 nm, b=200 nm and c=100 nm. Thus, the global level difference is a−c=200 nm.
As explained above, when memory cell array portions with different array surface area and peripheral circuit portions are both present, then there are regions at which the leveling of steps is accelerated and other regions that are polished at the polishing speed of the solid film, and when looking at the entire wafer surface, the non-uniformities in the polishing speed are large. As a result, the global step difference is large, and it is difficult to eliminate insufficient polishing and avoid scratches both. Such insufficient polishing, peeling of the lower electrodes and scratches cause bit defects in the ferroelectric memory and lower the production yields.
Furthermore, the ferroelectric memory is a non-volatile memory that stores data for a predetermined period of time, and from which the data can be read out when necessary, so that it is preferable that the ferroelectric memory is fabricated uniformly. In particular, variations in the film thickness of the ferroelectric film due to recesses have a considerable influence on the reliability with which data is held and on the ferroelectric memory properties, so that they should be reduced to a minimum.
Moreover, in ferroelectric memories, the global step difference between the memory cell array portion and other portions (for example peripheral logic circuitry in system LSI with integrated FeRAM) may lead to an insufficient DOF (depth of focus) of lithography in the wiring step, and may result in shorts between conductors or variations in the wiring resistance, and may directly affect the production yield.